1. Field of the Invention
The present invention relates generally to semiconductor device technologies and, more particularly, to a semiconductor integrated circuit device having an interwire insulation structure formed by a damascene process during formation of multilayered wiring leads. This invention also relates to a method of making the semiconductor device.
2. Description of Related Art
In recent years, the quest for higher integration and performance in large-scale integrated (LSI) semiconductor circuit chips results in development of new microfabrication techniques. In particular, in order to achieve further enhanced performances of LSI chips, challenges are made to replace traditional conductive material, i.e., aluminum (Al), of electrical interconnect lead wires by low-resistance metallic material, such as copper or copper alloys (collectively referred to as “Cu” hereinafter). Cu has the difficulty of micropatterning by currently-established dry etch techniques, which are widely used to form Al-alloy on-chip wires. An approach to breaking through this difficulty is to employ what is called the damascene process, which includes the steps of depositing a Cu film on or above an insulative or dielectric film with grooves defined therein, and then removing selected portions of the Cu film other than those buried in the grooves by chemical-mechanical polish (CMP) techniques to thereby form a pattern of buried interconnect wires. The Cu film is typically formed by a process which includes forming a thin seed layer by sputter techniques and thereafter applying thereto electrolytic plating to thereby provide a stacked film having its thickness of about several hundreds of nanometer (nm). In the case of forming a multilayer Cu wiring pattern, the so-called dual-damascene process is employable. This process includes depositing a dielectric film on or above a lower-level wiring layer, defining therein through-going holes, known as “via holes,” and trench-like wiring grooves used for upper-level wiring leads, forming a layer of Cu wiring material to fill both the via holes and the trenches at a time, and performing planarization for removing an unnecessary surface portion of the Cu layer, thereby to form buried or “inlayed” interconnect wires.
Recently, it is under consideration to use an insulative material that is low in dielectric constant, k, for interlayer dielectric (ILD) films. More specifically, attempts are made to reduce the parasitic capacitance between adjacent wires by use of a “low-k” film having its relative dielectric constant k on the order of approximately 3.5 or below, which is less than that (4.2) of silicon oxides (SiO2). One low-k material already in use is fluorosilicate glass (FSG); however, this material has its limit in dielectric constant reduction from a viewpoint of film quality stabilities. The reducibility of relative dielectric constant k stays merely at about 4.2 to 3.3 of the prior art. While low-k film materials with relative dielectric constant k of 2.5 or less are also under development, most of them are porous materials with bubble-like holes or voids contained therein. These porous low-k (p-lowk) films are fabricated by coating or chemical vapor deposition (CVD) processes; however, resultant p-lowk films are lower in density than thermally oxidized silicon films. Additionally, those materials of relative dielectric constant k of 2.0 or below are less in applicability in view of their deficiency in etchability and mechanical strength properties.
Consequently, in order to further lower the dielectric constant of ILD films to an extent lower than that of the above-noted p-lowk film, an attempt is made to develop a technique for cavitating interwire portions—i.e., forming cavities between neighboring onchip wires. Such cavities are called the “air gaps” in the semiconductor device art. An exemplary method is disclosed in Published Unexamined Japanese Patent Application No. 9-237831 (JP-A-9-237831). This method as taught thereby includes the steps of forming a carbon (C) layer, defining therein wiring grooves, depositing Cu to fill these wire grooves, forming a silicon oxide film to “cap” an entire top surface of resultant structure, forming a pattern of underlayer wires, and applying ashing to the C layer for cavitation. After having formed the cavities, a multilayer wiring structure is formed.
Other air-gap forming techniques include a process for defining air gaps in a dielectric film at its selected portions spaced far from via plugs (for example, see JP-A-2004-153280), and a process of forming air gaps in a single wiring layer at portions in dielectric film regions thereof in such a manner that these air gaps are surrounded by a silicon nitride film (see JP-A-2003-60032).
Unfortunately, the prior known processes are encountered with a problem which follows. In cases where a multilayer wiring structure is formed after having formed the air gaps between the underlayer wires as in the prior art, when defining via holes corresponding thereto in a dielectric film formed to overlie the underlayer wires, the via holes can deviate in position from their corresponding underlayer wires, causing misalignment therebetween. Once such misalignment occurs, the via holes behave to penetrate and burst through an ILD film, resulting in unwanted pass-through toward the underlying air gaps between wires. This “via-hole penetration” problem leads to creation of abnormal pattern shapes, which in turn makes it impossible to form any intended wires: as a matter of course, the parasitic capacitance reduction is by no means achievable. In other words, with the above-noted techniques for forming a multilayer wiring structure after formation of air gaps between underlayer wires, any misalignment with underlayer wires is hardly tolerable, which spoils the effective utilizability of air gap structures. Especially, in case via holes and trenches are defined with increased precision in a dielectric film overlying the underlayer wires, the difficulty becomes more serious because the etching depth required becomes larger than that in the case of forming the via holes only.
Even when considering a single wiring layer, the technique for forming silicon nitride film-surrounded air gaps in a wiring layer at portions of its dielectric film regions is faced with difficulties in reducing the parasitic capacitance sufficiently. One reason of this is that those regions in which the air gaps are to be formed are mere portions of the dielectric film region of the wiring layer. Another reason is that the air gaps formed are surrounded by the silicon nitride film, which is high in dielectric constant.